The present invention relates generally to CMOS integrated circuit design and fabrication, and, more particularly, to a method for compensating key circuit design parameters that may vary from one semiconductor wafer to the next.
The fabrication of a semiconductor integrated circuit (IC) relies on successful exploitation of the electrical characteristics of active devices, such as transistors, and passive devices, such as resistors, capacitors, and inductors, in a wide variety of circuit topologies. In order for the IC to produce desired electrical performance, each of its constituent circuit solutions exercises fundamental parameters of the devices offered in the CMOS process.
As examples, some critical electrical MOSFET parameters include, but are not limited to, threshold voltage (Vth), transconductance (gm), width of channel (W), length of channel (L) and oxide thickness (tox). These electrical parameters are defined by the physics of the methods and materials used to fabricate the IC. For example, Vth is a function of doping concentrations, equilibrium electrostatic potential, and a number of other intrinsic properties of the semiconductor wafer.
As is well known, each intrinsic physical property of the semiconductor wafer exhibits some statistical variation, which, for a tightly controlled process, is a Gaussian distribution. While, from one wafer-lot to the next, some physical parameters track closely, a large number do not. In this context, the term xe2x80x9ctrackxe2x80x9d refers to correlation between changes in one parameter and another. In order to produce electrical model parameters for a given semiconductor process, the IC foundry utilizes mathematical/empirical methods to process parametric data from thousands of wafers. Reflecting the statistical nature of the physical properties of the wafers, the extracted electrical parameters also exhibit statistical variation.
To illustrate this point, an average BSIM3v3 MOSFET model contains about 200 electrical parameters. As noted above, many of these electrical model parameters are uncorrelated. The statistical variations, coupled with parameter xe2x80x9cuncorrelatedness,xe2x80x9d lead to large changes in circuit performance parameters from one wafer-lot to another. For example, the center-frequency of a voltage controlled oscillator (VCO), nominally designed for 200 MHz, may be 50 MHz for ICs in one wafer-lot and 500 MHz for ICs in another wafer-lot. Such wide variation in electrical performance parameters is undesirable in many circuit applications.
There are a number of widely used methods for making circuit performance parameters insensitive to process variation. One expensive method is external trimming; i.e., laser wafer trimming, electrical and other fuses, or external digital correction through a digital signal processor (DSP). Another common method is to extend the range of the circuit performance parameters to allow for very wide tolerances. For example, one could use the VCO discussed hereinabove in a phase locked loop (PLL) application. However, such wide variations penalize circuit performance. In the case of a PLL, wide variation in VCO tuning range leads to such problems as excessive phase noise, excessive power consumption, and poor lock-up times.
In light of the foregoing, the invention provides an efficient method for automatic process compensation of circuit performance parameters, thereby eliminating costly trimming methods or performance degradation attributed to designing for large parameter tolerances.
Generally, the first embodiment of the system of the invention utilizes the difference in voltages between two identical diode-connected MOSFETs which are biased with currents that are known to be different in value. To the first order, the voltage difference tracks variation in transconductance for a given class of MOSFETs (N-MOSFETs or P-MOSFETs) across a given IC. For a given IC, a designer selects a dominant device-type that strongly influences the architectures of circuits implemented on the IC. This dominant device-type is determined by the 2 diode-connected MOSFETs used in the process detection/compensation circuit. The voltage-difference, xcex94VGS, of the two diode connected MOSFETs is then determined, being inversely proportional to the transconductance, hereinafter gm, of the first of the two diode-connected MOSFETs, which is also biased with a current, ID. Herein, xcex94VGS is also referred to as the xe2x80x9cprocess-state sensor.xe2x80x9d
A variable, , represents some circuit performance parameter, such as, but not limited to, the center-frequency of a VCO, or the bandwidth of an amplifier. The circuit designer then derives a relationship that embodies a direct proportionality between gm and . Thus, for the given class of dominant devices, a relationship is established between xcex94VGS, the process-state sensor, and the circuit performance parameter, , and as a result, the process dependent parameter, gm, is eliminated. Process compensation is then implemented, wherein a comparator compares known reference voltages with xcex94VGS. The outputs of the comparator are latched into digital decoding logic which provides coarse steering (process compensation) current to a functional circuit, thereby centering the circuit with respect to process. Thus, the circuit designer can realize circuit designs that utilize the given class of dominant design devices, to obtain process independent design parameters.
The invention has numerous advantages, a few of which are delineated hereinafter as examples. Note that the embodiments of the invention described herein possess one or more, but not necessarily all, of the advantages set out hereafter.
One advantage of the invention is that it allows an IC designer to center IC performance parameters very close to a Guassian nominal without resorting to costly trimming. This allows the IC designer to seek optimum circuit performance within a narrow, tightly controlled model space.
Another advantage of the present invention is that it provides a method of making IC electrical performance parameters process independent with minimal increase to the power consumption of the IC.
Another advantage of the present invention is that it eliminates a large amount of design-time required to produce a robust circuit design through numerous process-corner simulations. Therefore, the designer need not focus on exhaustive verification simulations in order to ensure that the circuit performs as expected in every comer of the model space.
Another advantage of the present invention is that it does not require external control through a DSP. All correction is done automatically on-chip.
Other features and advantages of the present invention will become apparent to one of reasonable skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional objects, features, and advantages be included herein within the scope of the present invention, as defined by the claims.